1. Field of the Invention
The invention relates to memory device, and in particular, to a control method for synchronous dynamic random access memory (SDRAM).
2. Description of the Related Art
FIG. 1a shows a conventional memory control timing sequence. In a SDRAM, a memory controller receives data access requests such as requests for reading/writing a specific address, and delivers corresponding commands to a memory device storing the requested data. A memory device typically comprises four or eight banks. A bank is a storage array formed by rows and columns with data bits stored therein. In each bank, only one row can be activated at a specific time, therefore, at most a total of eight rows are simultaneously activated in a memory device comprising eight banks. To active a row in a bank, the memory controller delivers an ACTIVE command to the memory device through a command bus comprising CS/RAS/CAS/WE wires, with the row address delivered through an address bus simultaneously. An activation typically consumes three clock cycles. After the row activation, the memory device delivers a READ/WRITE command to access the data according to a column address delivered through the address bus at the same time. The accessed row remains activated until another row in the same bank is requested for access. A PRECHARGE command is utilized to deactivate the first row before activating the second row, which typically consumes three clock cycles.
As shown in FIG. 1a, a plurality of commands are delivered through the command bus RAS/CAS/WE sequentially, with corresponding row addresses and column addresses delivered through an address bus. At time T1, a PRECHARGE command 110 is delivered to deactivate a first row in a bank BA0. In the meantime, a don't care signal 100 is delivered through the address bus. Thereafter, at time T4, an ACTIVE command 112 is delivered to activate a second row in the bank BA0, with a second row address 116 delivered through the address bus. At time T7, a READ command 114 is delivered to read a column in the activated row of the bank BA0, with the column address 118 delivered through the address bus. At time T8, another PRECHARGE command 120 deactivates a third row in bank BA1, and similarly, the corresponding ACTIVE command 122 and READ command 124 are delivered at time T11 and T14 to read data from the bank BA1. In this way, a command bus consumes fourteen cycle times to deliver six commands in which eight cycle times are idle, thus the bus utility is inefficient.
FIG. 1b shows another conventional memory command timing sequence. The bus utility is enhanced by interleaving different bank commands to avoid idle states. The PRECHARGE command 120 for bank BA1 is delivered at time T2, and the PRECHARGE command 130 for bank BA2 is delivered at time T3. Similarly, times T5 and T6 deliver ACTIVE commands for banks BA1 and BA2, and times T8 and T9 deliver READ commands for banks BA1 and BA2. In this way, the bus is fully utilized during time T1 to T9. At time T10, however, the access for a bank BA3 still comprise idle cycle times, for example, T11, T12, T14, and T15 in FIG. 1b. Thus, at most three banks (BA0, BA1 and BA2) can be accessed in succession.
FIG. 2 is a flowchart of conventional memory control. In step 202, the memory controller is initialized by receiving data access requests. In step 204, the memory controller determines whether the bank containing the requested data is activated. If not, the process proceeds to step 206 to activate the bank and perform a read/write operation in step 214. If the bank is activated in step 204, the process proceeds to step 208 to determine whether the requested row is same as the previously activated row. If yes, The read/write operation is directly performed in step 214. If not, the process proceeds to step 210 to send a PRECHARGE command to deactivate the previously activated row, and then send an ACTIVE command to activate the currently requested row in step 212 followed by step 214. The memory control operation ends with step 216.
In this way, a previously activated row must be deactivated before activating a currently requested row in the same bank, thus two commands are required to complete the operation, a PRECHARGE command for the previously activated row and an ACTIVE command for the currently requested row.